ISCA 2017

<html> <h2>Tutorials and Workshops:</h2> </html> [[http://isca17.ece.utoronto.ca/doku.php?id=wiki:tutorials|Tutorials]] [[http://isca17.ece.utoronto.ca/doku.php?id=wiki:workshops|Workshops]] <html> <h2>Main Program (tentative):</h2> <div lang="TR" link="blue" vlink="purple"> <div> <table border="0" cellpadding="0"> <tr> <td style="padding:.75pt .75pt .75pt .75pt"></td> </tr> </table> <table border="0" cellpadding="0"> <tr> <td style="padding:.75pt .75pt .75pt .75pt"> <table border="1" cellspacing="5" cellpadding="0" width="961" style="width:721.1pt"> <tr style="height:10.95pt"> <td width="952" colspan="5" style="width:713.7pt;border:solid #7f7f7f 2.25pt;background:#5e0d0d;padding:0cm 5.4pt 0cm 5.4pt;height:10.95pt"> Sunday, June 25, 2017 </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> PM </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> TBA </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Reception </td> </tr> <tr style="height:10.95pt"> <td width="952" colspan="5" style="width:713.7pt;border:solid #7f7f7f 2.25pt;background:#5e0d0d;padding:0cm 5.4pt 0cm 5.4pt;height:10.95pt"> Monday, June 26, 2017 </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> AM </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 8:15-8:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Welcoming Remarks </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 8:30-9:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Keynote 1</a>: TBA, Marc Bohr, Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 9:30-10:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Lightning Talks Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 10:30-11:00 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Break </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 11:00-12:00 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Session 1: Machine Learning 1 Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> PM </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 12:00-1:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Lunch </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 1:30-2:30 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 2A: IoT Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 2B: Security 1 Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 2:30-3:30 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 3A: Power and Energy Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 3B: Parallelism 1 Chair: </td> </tr> <tr> <td rowspan="2" style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" rowspan="2" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 3:30-4:00 </td> </tr> <tr> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Break </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 4:00-5:40 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 4A: Reliability Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 4B: GPUs Chair: </td> </tr>  <tr style="height:10.95pt"> <td width="952" colspan="5" style="width:713.7pt;border:solid #7f7f7f 2.25pt;background:#5e0d0d;padding:0cm 5.4pt 0cm 5.4pt;height:10.95pt"> Tuesday, June 27, 2017 </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> AM </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 8:30-9:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Keynote 2</a>: TBA, Partha Ranganathan, Google Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 9:30-10:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Lightning Talks Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 10:30-11:00 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Break </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 11:00-12:00 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Session 5: Security Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> PM </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 12:00-2:00 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Lunch </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 2:00-3:20 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 6A: Accelerator Design Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 6B: Virtualization and Translation Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 3:20-4:00 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 7A: Architectural support for Languages Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 7B: Datacenters Chair: </td> </tr> <tr> <td rowspan="2" style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" rowspan="2" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 4:00-4:15 </td> </tr> <tr> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Break </td> </tr> <tr> <td rowspan="2" style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" rowspan="2" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 4:15-5:30 </td> </tr> <tr> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Panel </td> </tr> <tr> <td rowspan="2" style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" rowspan="2" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 6:00- </td> </tr> <tr> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Excursion </td> </tr> <tr style="height:10.95pt"> <td width="952" colspan="5" style="width:713.7pt;border:solid #7f7f7f 2.25pt;background:#5e0d0d;padding:0cm 5.4pt 0cm 5.4pt;height:10.95pt"> Wednesday, June 28, 2017 </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> AM </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 9:00-10:00 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 8A</a>: Machine Learning 2 Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 8B</a>: Parallelism 2 Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 10:00-10:30 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Break </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"></td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 10:30-11:50 </td> <td width="361" style="width:270.55pt;padding:0cm 0cm 0cm 0cm"> Session 9A</a>: Memory Systems Chair: </td> <td width="462" colspan="2" style="width:346.75pt;padding:0cm 0cm 0cm 0cm"> Session 9B</a>: Network-on-Chip Chair: </td> </tr> <tr> <td style="padding:0cm 0cm 0cm 0cm"> </td> <td width="87" style="width:65.35pt;padding:0cm 0cm 0cm 0cm"> 11:50-12:00 </td> <td width="828" colspan="3" style="width:621.0pt;padding:0cm 0cm 0cm 0cm"> Conference Closing </td> </tr> </table> </td> </tr> </table> Monday, June 26, 2017 Keynote 1: , Marc Bohr, Intel Chair: <a name="session1a"></a>Monday, 11:00am-12:00pm Session 1: Machine Learning 1 Chair: · In-Datacenter Performance Analysis of a Tensor Processing Unit, Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Daniel Killebrew, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg, Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, and Doe Hyun Yoon (Google) · SCALEDEEP: A Scalable Compute Architecture for Learning and Evaluating Deep Networks, Swagath Venkataramani§, Ashish Ranjan§, Sasikanth Avancha‡, Ashok Jagannathan‡, Anand Raghunathan§, Subarno Banerjee‡, Dipankar Das‡, Ajaya Durg‡, Dheemanth Nagaraj‡, Bharat Kaul‡, and Pradeep Dubey‡ (§ School of ECE, Purdue University, ‡ Parallel Computing Lab, Intel Corporation) · SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks, Angshuman Parashar†, Minsoo Rhu†, Anurag Mukkara‡, Antonio Puglielli∗, Rangharajan Venkatesan†, Brucek Khailany†, Joel Emer†‡, Stephen W. Keckler†, and William J. Dally†⋄ (NVIDIA† Massachusetts Institute of Technology‡ UC-Berkeley∗ Stanford University⋄) <a name="session1a"></a>Monday, 1:30pm-2:30pm Session 2A: IoT Chair: · Bespoke Processors for Applications with Ultra-low Area and Power Constraints, Hari Cherupalli (University of Minnesota), Henry Duwe, Weidong Ye, Rakesh Kumar (University of Illinois), John Sartori (University of Minnesota) · A Programmable Galois Field Processor for the Internet of Things, Yajing Chen, Shengshuo Lu, Cheng Fu, David Blaauw, Ronald Dreslinski Jr, Trevor Mudge, and Hun-Seok Kim (University of Michigan, Ann Arbor) · XPro: A Cross-End Processing Architecture for Data Analytics in Wearables, Aosen Wang (State University of New York at Buffalo), Lizhong Chen (Oregon State University), Wenyao Xu (State University of New York at Buffalo) <a name="session1a"></a>Monday, 1:30pm-2:30pm Session 2B: Security 1 Chair: · Regaining Lost Cycles with HotCalls: A Fast Interface for SGX Secure Enclaves, Or Weisse, Valeria Bertacco, Todd Austin (University of Michigan) · InvisiMem: Smart Memory Defenses for Memory Bus Side Channel, Shaizeen Aga and Satish Narayanasamy (University of Michigan, Ann Arbor) · ObfusMem: A Low-Overhead Access Obfuscation for Trusted Memories, Amro Awad (Sandia National Laboratories), Yipeng Wang (North Carolina State University), Deborah Shands (National Science Foundation), Yan Solihin (North Carolina State University) <a name="session1a"></a>Monday, 2:30pm-3:30pm Session 3A: Power and Energy Chair: · ThermoGater: Thermally-Aware On-Chip Voltage Regulation, S. Karen Khatamifard* Longfei Wang† Weize Yu† Selçuk Köse† Ulya R. Karpuzcu* (* University of Minnesota † University of South Florida ) · PowerChief: Intelligent Power Allocation for Multi-Stage Applications to Improve Responsiveness on Power Constrained CMP, Hailong Yang†, Quan Chen⋄, Moeiz Riaz⋆, Zhongzhi Luan†, Lingjia Tang⋆, Jason Mars⋆ (School of Computer Science and Engineering, Beihang University† Department of Computer Science and Engineering, Shanghai Jiao Tong University⋄, Department of Computer Science, University of Michigan - Ann Arbor⋆) · CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures, Gokul Subramanian Ravi, Mikko H. Lipasti (Department of Electrical and Computer Engineering, University of Wisconsin - Madison) <a name="session1a"></a>Monday, 2:30pm-3:30pm Session 3B: Parallelism 1 Chair: · Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems, Matthew D. Sinclair, Johnathan Alsop, Sarita V. Adve (University of Illinois at Urbana-Champaign) · Hiding the Long Latency of Persist Barriers Using Speculative Execution, Seunghee Shin, James Tuck, Yan Solihin (Dept. of Electrical and Computer Engineering North Carolina State University) · Non-Speculative Load-Load Reordering in TSO, Alberto Ros (Department of Computer Engineering University of Murci), Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras (Department of Information Technology Uppsala University, Sweden) <a name="session1a"></a>Monday, 4:00pm-5:40pm Session 4A: Reliability Chair: · MTraceCheck: Validating Non-Deterministic Behavior of Memory Consistency Models in Post-Silicon Validation, Doowon Lee, Valeria Bertacco (University of Michigan) · Redundant Memory Array Architecture for Efficient Selective Protection, Ruohuang Zheng, Michael C. Huang (University of Rochester) · Clank: Architectural Support for Intermittent Computation, Matthew Hicks (Virginia Tech) · MeRLiN: Exploiting Dynamic Instruction Behavior for Fast and Accurate Microarchitecture Level Reliability Assessment, Manolis Kaliorakis, Dimitris Gizopoulos (Department of Informatics & Telecommunications University of Athens, Greece), Ramon Canal, Antonio Gonzalez (Computer Architecture Department Universitat Politecnica de Catalunya, Spain) · The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions, Minesh Patel§‡ Jeremie S. Kim‡§ Onur Mutlu§‡ (§ETH Zurich ‡Carnegie Mellon University) <a name="session1a"></a>Monday, 4:00pm-5:40pm Session 4B: GPUs Chair: · Quality of Service Support for Fine-Grained Sharing on GPUs, Zhenning Wang (Department of Computer Science Shanghai Jiao Tong University), Jun Yang, Rami Melhem, Bruce Childers, Youtao Zhang (University of Pittsburgh), Minyi Guo (Shanghai Jiao Tong University) · Accelerating GPU Hardware Transactional Memory with Snapshot Isolation, Sui Chen, Lu Peng, Samuel Irving (Division of Electrical & Computer Engineering Louisiana State University) · Decoupled Affine Computation for SIMT GPUs, Kai Wang, Calvin Lin (Department of Computer Science The University of Texas at Austin) · Access Pattern-Aware Cache Management for Improving Data Utilization in GPU, Gunjae Koo∗, Yunho Oh†, Won Woo Ro†, Murali Annavaram∗ (∗University of Southern California, †Yonsei University) · MCM-GPU: Multi-Chip-Module GPUs for Continued Performance Scalability, Akhil Arunkumar‡, Evgeny Bolotin†, Benjamin Cho∓, Ugljesa Milic+, Eiman Ebrahimi†, Oreste Villa†, Aamer Jaleel†, Carole-Jean Wu‡, David Nellans† (Arizona State University‡ NVIDIA† University of Texas at Austin∓ Barcelona Supercomputing Center / Universitat Politecnica de Catalunya+) Tuesday, June 27, 2017 Keynote 2: , Parthasarathy Ranganathan, Google Chair: <a name="session1a"></a>Tuesday, 11:00am-12:00pm Session 5: Security 2 Chair: · EDDIE: EM-Based Detection of Deviations in Program Execution, Alireza Nazari∗, Nader Sehatbakhsh†, Monjur Alam◁, Alenka Zajic⋄, Milos Prvulovic∓ (Georgia Institute of Technology) · Secure Hierarchy-Aware Cache Replacement Policy (SHARP): Defending Against Cache-Based Side Channel Attacks, Mengjia Yan, Bhargava Gopireddy, Thomas Shull, Josep Torrellas (University of Illinois at Urbana-Champaign) · Lemonade from Lemons: Harnessing Device Wearout to Create Limited-Use Security Architectures, Zhaoxia Deng, (Department of Computer Science, University of California, Santa Barbara), Ariel Feldman, Stuart A. Kurtz, Frederic T. Chong (Department of Computer Science, University of Chicago) <a name="session1a"></a>Tuesday, 2:00pm-3:20pm Session 6A: Accelerator Design Chair: · LogCA: A High-Level Performance Model for Hardware Accelerators, Muhammad Shoaib, Bin Altaf, David A. Wood (AMD Research Advanced Micro Devices, Inc., Computer Sciences Department University of Wisconsin-Madison) · Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware, Zhaoshi Li1, Leibo Liu1*, Yangdong Deng2, Shouyi Yin1, Yao Wang1, Shaojun Wei1, (1 National Laboratory for Information Science and Technology, Tsinghua University, 2 School of Software, Tsinghua University) · A Programmable Hardware Accelerator for Simulating Dynamical Systems, Jaeha Kung, Yun Long, Duckhwan Kim, Saibal Mukhopadhyay (Georgia Institute of Technology) · Stream-Dataflow Acceleration, Tony Nowatzki∗†, Vinay Gangadhar†, Newsha Ardalani†, Karthikeyan Sankaralingam† (∗University of California, Los Angeles † University of Wisconsin, Madison) <a name="session1a"></a>Tuesday, 2:00pm-3:20pm Session 6B: Virtualization and Translation Chair: · Hardware Translation Coherence for Virtualized Systems, Zi Yan, Ján Veselý, Guilherme Cox, Abhishek Bhattacharjee (Department of Computer Science, Rutgers University) · Hybrid TLB Coalescing: Improving TLB Translation Coverage under Diverse Fragmented Memory Allocations, Chang Hyun Park, Taekyung Heo, Jungi Jeong, Jaehyuk Huh (School of Computing, KAIST) · Do-It-Yourself Virtual Memory Translation, Hanna Alam1, Tianhao Zhang2, Mattan Erez2, Yoav Etsion1 (Technion - Israel Institute of Technology 1, The University of Texas at Austin 2) · Rethinking TLB Designs in Virtualized Environments: A Very Large Part-of-Memory TLB, Jee Ho Ryoo, Nagendra Gulur†, Shuang Song, Lizy K. John (The University of Texas at Austin, †Texas Instruments) <a name="session1a"></a>Tuesday, 3:20pm-4:00pm Session 7A: Architectural support for Languages Chair: · Language-level persistency, Aasheesh Kolli, Vaibhav Gogte, Ali Saidi, Stephan Diestelhorst, Peter M. Chen, Satish Narayanasamy, Thomas F. Wenisch (University of Michigan, ARM) · ShortCut: Architectural Support for Fast Object Access in Scripting Languages, Jiho Choi, Thomas Shull, Maria J. Garzaran, Josep Torrellas (University of Illinois at Urbana-Champaign) <a name="session1a"></a>Tuesday, 3:20pm-4:00pm Session 7B: Datacenters Chair: · Architectural Support for Server-Side PHP Processing, Dibakar Gope, David J. Schlais, Mikko H. Lipasti (Department of Electrical and Computer Engineering University of Wisconsin - Madison) · HeteroOS - OS design for heterogeneous memory management in datacenter, Sudarsun Kannan1, Ada Gavrilovska2, Vishal Gupta3, Karsten Schwan2 (1 Department of Computer Sciences, University of Wisconsin-Madison, 2 School of Computer Science, Georgia Tech, 3 VMWare) Wednesday, June 28, 2017 <a name="session1a"></a>Wednesday, 9:00am-10:00am Session 8A: Machine Learning 2 Chair: · Maximizing CNN Accelerator Efficiency Through Resource Partitioning, Yongming Shen, Michael Ferdman, Peter Milder (Stony Brook University) · Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism, Jiecao Yu1, Andrew Lukefahr1, David Palframan2, Ganesh Dasika2, Reetuparna Das1, Scott Mahlke1 (1 University of Michigan, 2 ARM) · Understanding and Optimizing Asynchronous Low-Precision Stochastic Gradient Descent, Christopher De Sa, Matthew Feldman, Christopher Ré, Kunle Olukotun (Departments of Electrical Engineering and Computer Science Stanford University) <a name="session1a"></a>Wednesday, 9:00am-10:00am Session 8B: Parallelism 2 Chair: · Plasticine: A Reconfigurable Architecture for Parallel Patterns, Raghu Prabhakar, Yaqi Zhang, David Koeplinger, Matt Feldman, Tian Zhao, Stefan Hadjis, Ardavan Pedram, Christos Kozyrakis, Kunle Olukotun (Stanford University) · Fractal: An Execution Model for Fine-Grain Nested Speculative Parallelism, Suvinay Subramanian∗, Mark C. Jeffrey∗, Maleen Abeydeera∗, Hyun Ryong Lee∗, Victor A. Ying∗, Joel Emer∗†, Daniel Sanchez∗ (∗Massachusetts Institute of Technology †NVIDIA) · Parallel Automata Processor, Arun Subramaniyan, Reetuparna Das (University of Michigan-Ann Arbor) <a name="session1a"></a>Wednesday, 10:30am-11:50am Session 9A: Memory Systems Chair: · Viyojit: Decoupling Battery and DRAM Capacities for Battery-Backed DRAM, Rajat Kateja (Carnegie Mellon University), Anirudh Badam, Sriram Govindan, Bikash Sharma (Microsoft), Greg Ganger (Carnegie Mellon University) · DICE: Compressing DRAM Caches for Bandwidth and Capacity, Vinson Young, Prashant J. Nair, Moinuddin K. Qureshi (School of Electrical and Computer Engineering, Georgia Institute of Technology) · The Mondrian Data Engine, Mario Drumond, Alexandros Daglis, Nooshin Mirzadeh, Dmitrii Ustiugov, Javier Picorel, Babak Falsafi (EcoCloud, EPFL), Boris Grot (University of Edinburgh), Dionisios Pnevmatikatos (FORTH-ICS & ECE-TUC) · Jenga: Software-Defined Cache Hierarchies, Po-An Tsai (MIT CSAIL), Nathan Beckmann (CMU SCS), Daniel Sanchez (MIT CSAIL) <a name="session1a"></a>Wednesday, 10:30am-11:50am Session 9B: Network-on-Chip Chair: · APPROX-NoC: A Data Approximation Framework for Network-On-Chip Architectures, Rahul Boyapati, Jiayi Huang, Pritam Majumder, Ki Hwan, Yum Eun, Jung Kim (Texas A&M University) · There and Back Again: Optimizing the Interconnect in Networks of Memory Cubes, · Footprint: Regulating Routing Adaptiveness in Networks-on-Chip, Binzhang Fu, John Kim (SKL Computer Architecture ICT, CAS School of Computing, KAIST) · EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks, Masoumeh Ebrahimi⋆, Masoud Daneshtalab⋆† (Royal Institute of Technology, Sweden⋆ Mälardalen University, Sweden†) </html>